Merge pull request #326966 from hzeller/feature-20240713-rename-verilog-to-iverilog

verilog: rename to actual name iverilog
This commit is contained in:
Aleksana
2024-07-18 12:39:17 +08:00
committed by GitHub
11 changed files with 18 additions and 19 deletions
@@ -3,7 +3,7 @@
, fetchFromGitHub
, bison
, flex
, verilog
, iverilog
, which
}:
@@ -25,7 +25,7 @@ stdenv.mkDerivation rec {
];
buildInputs = [
verilog
iverilog
];
# the "translate" target both (a) builds the software and (b) runs
@@ -17,7 +17,7 @@
, zlib
, ghc
, gmp-static
, verilog
, iverilog
, asciidoctor
, texliveFull
, which
@@ -108,7 +108,7 @@ in stdenv.mkDerivation rec {
nativeCheckInputs = [
gmp-static
verilog
iverilog
];
checkTarget = "check-smoke"; # this is the shortest check but "check-suite" tests much more
+2 -2
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@@ -11,7 +11,7 @@
, readline
, symlinkJoin
, tcl
, verilog
, iverilog
, zlib
, yosys
, yosys-bluespec
@@ -147,7 +147,7 @@ in stdenv.mkDerivation (finalAttrs: {
checkTarget = "test";
doCheck = true;
nativeCheckInputs = [ verilog ];
nativeCheckInputs = [ iverilog ];
setupHook = ./setup-hook.sh;
@@ -9,7 +9,7 @@
find-libpython,
pytestCheckHook,
swig,
verilog,
iverilog,
ghdl,
}:
@@ -65,7 +65,7 @@ buildPythonPackage rec {
cocotb-bus
pytestCheckHook
swig
verilog
iverilog
ghdl
];
preCheck = ''
@@ -2,7 +2,7 @@
lib,
fetchFromGitHub,
buildPythonPackage,
verilog,
iverilog,
ghdl,
pytest,
pytest-xdist,
@@ -24,13 +24,13 @@ buildPythonPackage rec {
nativeCheckInputs = [
pytest
pytest-xdist
verilog
iverilog
ghdl
];
passthru = {
# If using myhdl as a dependency, use these if needed and not ghdl and
# verlog from all-packages.nix
inherit ghdl verilog;
inherit ghdl iverilog;
};
checkPhase = ''
runHook preCheck
@@ -5,7 +5,7 @@
pythonOlder,
jinja2,
ply,
verilog,
iverilog,
pytestCheckHook,
}:
@@ -24,13 +24,13 @@ buildPythonPackage rec {
patchPhase = ''
# The path to Icarus can still be overridden via an environment variable at runtime.
substituteInPlace pyverilog/vparser/preprocessor.py \
--replace "iverilog = 'iverilog'" "iverilog = '${verilog}/bin/iverilog'"
--replace "iverilog = 'iverilog'" "iverilog = '${iverilog}/bin/iverilog'"
'';
propagatedBuildInputs = [
jinja2
ply
verilog
iverilog
];
preCheck = ''
@@ -1,7 +1,7 @@
{ buildPythonPackage
, fetchPypi
, lib
, verilog
, iverilog
, verilator
, gnumake
, edalize
@@ -27,7 +27,7 @@ buildPythonPackage rec {
pythonImportsCheck = [ "fusesoc" ];
makeWrapperArgs = [ "--suffix PATH : ${lib.makeBinPath [ verilog verilator gnumake ]}"];
makeWrapperArgs = [ "--suffix PATH : ${lib.makeBinPath [ iverilog verilator gnumake ]}"];
meta = with lib; {
homepage = "https://github.com/olofk/fusesoc";
+1
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@@ -1442,6 +1442,7 @@ mapAliases ({
vdirsyncerStable = vdirsyncer; # Added 2020-11-08, see https://github.com/NixOS/nixpkgs/issues/103026#issuecomment-723428168
ventoy-bin = ventoy; # Added 2023-04-12
ventoy-bin-full = ventoy-full; # Added 2023-04-12
verilog = iverilog; # Added 2024-07-12
ViennaRNA = viennarna; # Added 2023-08-23
vikunja-api = throw "'vikunja-api' has been replaced by 'vikunja'"; # Added 2024-02-19
vikunja-frontend = throw "'vikunja-frontend' has been replaced by 'vikunja'"; # Added 2024-02-19
-2
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@@ -13892,8 +13892,6 @@ with pkgs;
verilator = callPackage ../applications/science/electronics/verilator { };
verilog = callPackage ../applications/science/electronics/verilog { };
versus = callPackage ../applications/networking/versus { };
vexctl = callPackage ../tools/security/vexctl { };
+1 -1
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@@ -8032,7 +8032,7 @@ self: super: with self; {
mygpoclient = callPackage ../development/python-modules/mygpoclient { };
myhdl = callPackage ../development/python-modules/myhdl {
inherit (pkgs) ghdl verilog;
inherit (pkgs) ghdl iverilog;
};
myhome = callPackage ../development/python-modules/myhome { };