diff --git a/pkgs/applications/science/electronics/vhd2vl/default.nix b/pkgs/applications/science/electronics/vhd2vl/default.nix index 078f5e951404..28656fe6e121 100644 --- a/pkgs/applications/science/electronics/vhd2vl/default.nix +++ b/pkgs/applications/science/electronics/vhd2vl/default.nix @@ -3,7 +3,7 @@ , fetchFromGitHub , bison , flex -, verilog +, iverilog , which }: @@ -25,7 +25,7 @@ stdenv.mkDerivation rec { ]; buildInputs = [ - verilog + iverilog ]; # the "translate" target both (a) builds the software and (b) runs diff --git a/pkgs/applications/science/electronics/verilog/default.nix b/pkgs/by-name/iv/iverilog/package.nix similarity index 100% rename from pkgs/applications/science/electronics/verilog/default.nix rename to pkgs/by-name/iv/iverilog/package.nix diff --git a/pkgs/development/compilers/bluespec/default.nix b/pkgs/development/compilers/bluespec/default.nix index edf0f03659b2..e761c8609e8b 100644 --- a/pkgs/development/compilers/bluespec/default.nix +++ b/pkgs/development/compilers/bluespec/default.nix @@ -17,7 +17,7 @@ , zlib , ghc , gmp-static -, verilog +, iverilog , asciidoctor , texliveFull , which @@ -108,7 +108,7 @@ in stdenv.mkDerivation rec { nativeCheckInputs = [ gmp-static - verilog + iverilog ]; checkTarget = "check-smoke"; # this is the shortest check but "check-suite" tests much more diff --git a/pkgs/development/compilers/yosys/default.nix b/pkgs/development/compilers/yosys/default.nix index 6af75057e898..f90b7b31bbcd 100644 --- a/pkgs/development/compilers/yosys/default.nix +++ b/pkgs/development/compilers/yosys/default.nix @@ -11,7 +11,7 @@ , readline , symlinkJoin , tcl -, verilog +, iverilog , zlib , yosys , yosys-bluespec @@ -147,7 +147,7 @@ in stdenv.mkDerivation (finalAttrs: { checkTarget = "test"; doCheck = true; - nativeCheckInputs = [ verilog ]; + nativeCheckInputs = [ iverilog ]; setupHook = ./setup-hook.sh; diff --git a/pkgs/development/python-modules/cocotb/default.nix b/pkgs/development/python-modules/cocotb/default.nix index f65b11c81ce2..e7a322dad473 100644 --- a/pkgs/development/python-modules/cocotb/default.nix +++ b/pkgs/development/python-modules/cocotb/default.nix @@ -9,7 +9,7 @@ find-libpython, pytestCheckHook, swig, - verilog, + iverilog, ghdl, }: @@ -65,7 +65,7 @@ buildPythonPackage rec { cocotb-bus pytestCheckHook swig - verilog + iverilog ghdl ]; preCheck = '' diff --git a/pkgs/development/python-modules/myhdl/default.nix b/pkgs/development/python-modules/myhdl/default.nix index ec9dfcaf8276..959856365d24 100644 --- a/pkgs/development/python-modules/myhdl/default.nix +++ b/pkgs/development/python-modules/myhdl/default.nix @@ -2,7 +2,7 @@ lib, fetchFromGitHub, buildPythonPackage, - verilog, + iverilog, ghdl, pytest, pytest-xdist, @@ -24,13 +24,13 @@ buildPythonPackage rec { nativeCheckInputs = [ pytest pytest-xdist - verilog + iverilog ghdl ]; passthru = { # If using myhdl as a dependency, use these if needed and not ghdl and # verlog from all-packages.nix - inherit ghdl verilog; + inherit ghdl iverilog; }; checkPhase = '' runHook preCheck diff --git a/pkgs/development/python-modules/pyverilog/default.nix b/pkgs/development/python-modules/pyverilog/default.nix index ba591fa9f53b..0868f7eadde5 100644 --- a/pkgs/development/python-modules/pyverilog/default.nix +++ b/pkgs/development/python-modules/pyverilog/default.nix @@ -5,7 +5,7 @@ pythonOlder, jinja2, ply, - verilog, + iverilog, pytestCheckHook, }: @@ -24,13 +24,13 @@ buildPythonPackage rec { patchPhase = '' # The path to Icarus can still be overridden via an environment variable at runtime. substituteInPlace pyverilog/vparser/preprocessor.py \ - --replace "iverilog = 'iverilog'" "iverilog = '${verilog}/bin/iverilog'" + --replace "iverilog = 'iverilog'" "iverilog = '${iverilog}/bin/iverilog'" ''; propagatedBuildInputs = [ jinja2 ply - verilog + iverilog ]; preCheck = '' diff --git a/pkgs/tools/package-management/fusesoc/default.nix b/pkgs/tools/package-management/fusesoc/default.nix index a3e397ae9391..26e27738d647 100644 --- a/pkgs/tools/package-management/fusesoc/default.nix +++ b/pkgs/tools/package-management/fusesoc/default.nix @@ -1,7 +1,7 @@ { buildPythonPackage , fetchPypi , lib -, verilog +, iverilog , verilator , gnumake , edalize @@ -27,7 +27,7 @@ buildPythonPackage rec { pythonImportsCheck = [ "fusesoc" ]; - makeWrapperArgs = [ "--suffix PATH : ${lib.makeBinPath [ verilog verilator gnumake ]}"]; + makeWrapperArgs = [ "--suffix PATH : ${lib.makeBinPath [ iverilog verilator gnumake ]}"]; meta = with lib; { homepage = "https://github.com/olofk/fusesoc"; diff --git a/pkgs/top-level/aliases.nix b/pkgs/top-level/aliases.nix index 3f8d064e7799..c6af4d9df512 100644 --- a/pkgs/top-level/aliases.nix +++ b/pkgs/top-level/aliases.nix @@ -1442,6 +1442,7 @@ mapAliases ({ vdirsyncerStable = vdirsyncer; # Added 2020-11-08, see https://github.com/NixOS/nixpkgs/issues/103026#issuecomment-723428168 ventoy-bin = ventoy; # Added 2023-04-12 ventoy-bin-full = ventoy-full; # Added 2023-04-12 + verilog = iverilog; # Added 2024-07-12 ViennaRNA = viennarna; # Added 2023-08-23 vikunja-api = throw "'vikunja-api' has been replaced by 'vikunja'"; # Added 2024-02-19 vikunja-frontend = throw "'vikunja-frontend' has been replaced by 'vikunja'"; # Added 2024-02-19 diff --git a/pkgs/top-level/all-packages.nix b/pkgs/top-level/all-packages.nix index d503b2b695ec..d9f7beef8610 100644 --- a/pkgs/top-level/all-packages.nix +++ b/pkgs/top-level/all-packages.nix @@ -13892,8 +13892,6 @@ with pkgs; verilator = callPackage ../applications/science/electronics/verilator { }; - verilog = callPackage ../applications/science/electronics/verilog { }; - versus = callPackage ../applications/networking/versus { }; vexctl = callPackage ../tools/security/vexctl { }; diff --git a/pkgs/top-level/python-packages.nix b/pkgs/top-level/python-packages.nix index 61f2bfd290c3..4ead26c9e215 100644 --- a/pkgs/top-level/python-packages.nix +++ b/pkgs/top-level/python-packages.nix @@ -8032,7 +8032,7 @@ self: super: with self; { mygpoclient = callPackage ../development/python-modules/mygpoclient { }; myhdl = callPackage ../development/python-modules/myhdl { - inherit (pkgs) ghdl verilog; + inherit (pkgs) ghdl iverilog; }; myhome = callPackage ../development/python-modules/myhome { };