Gaetan Lepage
2025-07-07 13:40:12 +02:00
parent 4d18d2d1ce
commit 5c40143e10
2 changed files with 19 additions and 30 deletions
+8 -6
View File
@@ -1,18 +1,20 @@
diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh
index ee299fc82..595cd3f88 100755
--- a/tests/cxxrtl/run-test.sh
+++ b/tests/cxxrtl/run-test.sh
@@ -5,7 +5,7 @@ set -ex
run_subtest () {
local subtest=$1; shift
- ${CC:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++
+ ${CXX:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++
./cxxrtl-test-${subtest}
}
@@ -14,4 +14,4 @@ run_subtest value_fuzz
# Compile-only test.
../../yosys -p "read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
../../yosys -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
-${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc
+${CXX:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc
diff --git a/tests/fmt/run-test.sh b/tests/fmt/run-test.sh
@@ -21,7 +23,7 @@ index 998047f83..2a4a59f01 100644
+++ b/tests/fmt/run-test.sh
@@ -51,7 +51,7 @@ test_cxxrtl () {
local subtest=$1; shift
../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc"
- ${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++
+ ${CXX:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++
@@ -29,7 +31,7 @@ index 998047f83..2a4a59f01 100644
iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v
./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log
@@ -69,7 +69,7 @@ diff iverilog-always_full.log iverilog-always_full-1.log
../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log
../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc"
-${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
+11 -24
View File
@@ -14,7 +14,6 @@
readline,
tcl,
zlib,
boost,
# tests
gtkwave,
@@ -86,13 +85,13 @@ let
in
stdenv.mkDerivation (finalAttrs: {
pname = "yosys";
version = "0.51";
version = "0.54";
src = fetchFromGitHub {
owner = "YosysHQ";
repo = "yosys";
tag = "v${finalAttrs.version}";
hash = "sha256-Y2Gf3CXd1em+4dlIo2+dwfZbqahM3kqG0rZUTjkIZak=";
hash = "sha256-yEAZvdBc+923a0OTtaCpTbrl33kcmvgwFlL5VEssHkQ=";
fetchSubmodules = true;
leaveDotGit = true;
postFetch = ''
@@ -110,20 +109,11 @@ stdenv.mkDerivation (finalAttrs: {
};
enableParallelBuilding = true;
nativeBuildInputs =
[
bison
flex
pkg-config
]
++ lib.optionals enablePython [
(python3.withPackages (
p: with p; [
pip
setuptools
]
))
];
nativeBuildInputs = [
bison
flex
pkg-config
];
propagatedBuildInputs =
[
@@ -131,24 +121,21 @@ stdenv.mkDerivation (finalAttrs: {
readline
tcl
zlib
]
++ lib.optionals enablePython [
(python3.withPackages (
pp: with pp; [
click
]
))
(boost.override {
enablePython = true;
python = python3;
})
]
++ lib.optionals enablePython [
python3.pkgs.boost
];
makeFlags = [ "PREFIX=${placeholder "out"}" ];
patches = [
./plugin-search-dirs.patch
./fix-clang-build.patch # see https://github.com/YosysHQ/yosys/issues/2011
./fix-clang-build.patch
];
postPatch = ''