Gaetan Lepage
93 lines
3.1 KiB
Nix
93 lines
3.1 KiB
Nix
{
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lib,
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buildPythonPackage,
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fetchPypi,
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# build-system
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setuptools,
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# tests
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ghdl,
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iverilog,
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pytestCheckHook,
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}:
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buildPythonPackage rec {
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pname = "myhdl";
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version = "0.11.51";
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pyproject = true;
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# No recent tags on GitHub
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src = fetchPypi {
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inherit pname version;
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hash = "sha256-nZEdYLRjk2rgS3byc4iu9oJazodnoNg63MBUMasGZiw=";
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};
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build-system = [
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setuptools
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];
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nativeCheckInputs = [
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ghdl
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iverilog
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pytestCheckHook
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];
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enabledTestPaths = [
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"myhdl/test"
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];
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disabledTestPaths = [
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# myhdl.CosimulationError: Premature simulation end
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# ----------------------------- Captured stdout call -----------------------------
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# binaryOps.o: Program not runnable, 2 errors.
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# ----------------------------- Captured stderr call -----------------------------
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# ../../../../cosimulation/icarus/myhdl.vpi: Unable to find module file `../../../../cosimulation/icarus/myhdl.vpi' or `../../../../cosimulation/icarus/myhdl.vpi.vpi'.
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# tb_binaryOps.v:24: Error: System task/function $from_myhdl() is not defined by any module.
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# tb_binaryOps.v:29: Error: System task/function $to_myhdl() is not defined by any module.
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"myhdl/test/conversion/toVerilog/test_GrayInc.py"
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"myhdl/test/conversion/toVerilog/test_RandomScrambler.py"
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"myhdl/test/conversion/toVerilog/test_always_comb.py"
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"myhdl/test/conversion/toVerilog/test_beh.py"
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"myhdl/test/conversion/toVerilog/test_bin2gray.py"
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"myhdl/test/conversion/toVerilog/test_dec.py"
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"myhdl/test/conversion/toVerilog/test_edge.py"
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"myhdl/test/conversion/toVerilog/test_fsm.py"
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"myhdl/test/conversion/toVerilog/test_hec.py"
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"myhdl/test/conversion/toVerilog/test_inc.py"
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"myhdl/test/conversion/toVerilog/test_loops.py"
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"myhdl/test/conversion/toVerilog/test_misc.py"
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"myhdl/test/conversion/toVerilog/test_ops.py"
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"myhdl/test/conversion/toVerilog/test_ram.py"
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"myhdl/test/conversion/toVerilog/test_rom.py"
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];
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disabledTests = [
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# myhdl.CosimulationError: Premature simulation end
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# ----------------------------- Captured stdout call -----------------------------
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# binaryOps.o: Program not runnable, 2 errors.
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# ----------------------------- Captured stderr call -----------------------------
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# ../../../../cosimulation/icarus/myhdl.vpi: Unable to find module file `../../../../cosimulation/icarus/myhdl.vpi' or `../../../../cosimulation/icarus/myhdl.vpi.vpi'.
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# tb_binaryOps.v:24: Error: System task/function $from_myhdl() is not defined by any module.
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# tb_binaryOps.v:29: Error: System task/function $to_myhdl() is not defined by any module.
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"TestInc"
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"TestInfer"
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"testAugmOps"
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"testBinaryOps"
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"testUnaryOps"
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];
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passthru = {
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# If using myhdl as a dependency, use these if needed and not ghdl and
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# verlog from all-packages.nix
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inherit ghdl iverilog;
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};
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meta = {
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description = "Free, open-source package for using Python as a hardware description and verification language";
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homepage = "https://www.myhdl.org/";
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license = lib.licenses.lgpl21;
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maintainers = with lib.maintainers; [ doronbehar ];
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};
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}
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