62 lines
1.6 KiB
Diff
62 lines
1.6 KiB
Diff
From 778cb2ed0d56614fd06d2129398799e46ff51720 Mon Sep 17 00:00:00 2001
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From: Marcin Serwin <marcin@serwin.dev>
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Date: Mon, 3 Nov 2025 22:25:10 +0100
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Subject: [PATCH] Add aarch64-linux support
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Signed-off-by: Marcin Serwin <marcin@serwin.dev>
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---
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src/Etterna/Models/Misc/StageStats.cpp | 23 +++++++++++++++++++++--
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1 file changed, 21 insertions(+), 2 deletions(-)
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diff --git a/src/Etterna/Models/Misc/StageStats.cpp b/src/Etterna/Models/Misc/StageStats.cpp
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index 0c70cf25ae..671717505d 100644
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--- a/src/Etterna/Models/Misc/StageStats.cpp
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+++ b/src/Etterna/Models/Misc/StageStats.cpp
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@@ -19,8 +19,9 @@
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#include "Etterna/Singletons/GameManager.h"
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#include "Etterna/Models/NoteData/NoteDataUtil.h"
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-#if !( defined(_WIN32) || defined(__APPLE__))
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- #include <cpuid.h> //We only use cpuid.h on Linux :)
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+#if !( defined(_WIN32) || defined(__APPLE__)) \
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+ && (defined(__x86_64__) || defined(__i386__))
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+ #include <cpuid.h> //We only use cpuid.h on x86 Linux :)
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#endif
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#ifdef _WIN32
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@@ -236,6 +237,8 @@ getCpuHash()
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#else // !DARWIN
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+#if defined(__x86_64__) || defined(__i386__)
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+
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uint16_t
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getCpuHash()
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{
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@@ -248,6 +251,22 @@ getCpuHash()
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return hash;
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}
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+
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+#else // !x86
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+
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+uint16_t
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+getCpuHash()
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+{
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+ // https://www.kernel.org/doc/html/v6.17/arch/arm64/cpu-feature-registers.html
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+ uint64_t midr = 0;
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+ asm("mrs %0, MIDR_EL1" : "=r"(midr));
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+
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+ // Only leave implementer, variant, and architecture bits.
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+ // See https://developer.arm.com/documentation/ddi0601/2025-09/AArch64-Registers/MIDR-EL1--Main-ID-Register?lang=en
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+ return midr >> 16;
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+}
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+
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+#endif // !x86
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#endif // !DARWIN
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std::string
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--
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2.51.0
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