From 2b47345ff54be47f71000722aafaf3d0a124c35c Mon Sep 17 00:00:00 2001 From: Connor Baker Date: Tue, 31 Oct 2023 14:43:55 +0000 Subject: [PATCH] glibc: add NVCC include guards to fix ARM CUDA compilation --- ...math-vector.h-add-NVCC-include-guard.patch | 37 +++++++++++++++++++ pkgs/development/libraries/glibc/common.nix | 14 ++++++- 2 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 pkgs/development/libraries/glibc/0001-aarch64-math-vector.h-add-NVCC-include-guard.patch diff --git a/pkgs/development/libraries/glibc/0001-aarch64-math-vector.h-add-NVCC-include-guard.patch b/pkgs/development/libraries/glibc/0001-aarch64-math-vector.h-add-NVCC-include-guard.patch new file mode 100644 index 000000000000..234bc1943c9a --- /dev/null +++ b/pkgs/development/libraries/glibc/0001-aarch64-math-vector.h-add-NVCC-include-guard.patch @@ -0,0 +1,37 @@ +From 44d0a3a9bd8c6fe59f6ccb44206a50a900bfcf4a Mon Sep 17 00:00:00 2001 +From: Connor Baker +Date: Tue, 31 Oct 2023 14:30:24 +0000 +Subject: [PATCH] aarch64/math-vector.h: add NVCC include guard + +--- + sysdeps/aarch64/fpu/bits/math-vector.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h +index 7c200599c1..583a426494 100644 +--- a/sysdeps/aarch64/fpu/bits/math-vector.h ++++ b/sysdeps/aarch64/fpu/bits/math-vector.h +@@ -25,17 +25,17 @@ + /* Get default empty definitions for simd declarations. */ + #include + +-#if __GNUC_PREREQ(9, 0) ++#if __GNUC_PREREQ(9, 0) && !defined(__CUDACC__) + # define __ADVSIMD_VEC_MATH_SUPPORTED + typedef __Float32x4_t __f32x4_t; + typedef __Float64x2_t __f64x2_t; +-#elif __glibc_clang_prereq(8, 0) ++#elif __glibc_clang_prereq(8, 0) && !defined(__CUDACC__) + # define __ADVSIMD_VEC_MATH_SUPPORTED + typedef __attribute__ ((__neon_vector_type__ (4))) float __f32x4_t; + typedef __attribute__ ((__neon_vector_type__ (2))) double __f64x2_t; + #endif + +-#if __GNUC_PREREQ(10, 0) || __glibc_clang_prereq(11, 0) ++#if (__GNUC_PREREQ(10, 0) || __glibc_clang_prereq(11, 0)) && !defined(__CUDACC__) + # define __SVE_VEC_MATH_SUPPORTED + typedef __SVFloat32_t __sv_f32_t; + typedef __SVFloat64_t __sv_f64_t; +-- +2.42.0 + diff --git a/pkgs/development/libraries/glibc/common.nix b/pkgs/development/libraries/glibc/common.nix index 646242de6119..3e17817c0bab 100644 --- a/pkgs/development/libraries/glibc/common.nix +++ b/pkgs/development/libraries/glibc/common.nix @@ -97,6 +97,18 @@ stdenv.mkDerivation ({ */ ./reenable_DT_HASH.patch ] + /* NVCC does not support ARM intrinsics. Since is pulled in by almost + every HPC piece of software, without this patch CUDA compilation on ARM + is effectively broken. See + https://forums.developer.nvidia.com/t/nvcc-fails-to-build-with-arm-neon-instructions-cpp-vs-cu/248355/2. + */ + ++ ( + let + isAarch64 = stdenv.buildPlatform.isAarch64 || stdenv.hostPlatform.isAarch64; + isLinux = stdenv.buildPlatform.isLinux || stdenv.hostPlatform.isLinux; + in + lib.optional (isAarch64 && isLinux) ./0001-aarch64-math-vector.h-add-NVCC-include-guard.patch + ) ++ lib.optional stdenv.hostPlatform.isMusl ./fix-rpc-types-musl-conflicts.patch ++ lib.optional stdenv.buildPlatform.isDarwin ./darwin-cross-build.patch; @@ -276,7 +288,7 @@ stdenv.mkDerivation ({ license = licenses.lgpl2Plus; - maintainers = with maintainers; [ eelco ma27 ]; + maintainers = with maintainers; [ eelco ma27 connorbaker ]; platforms = platforms.linux; } // (args.meta or {}); })